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Final Electrical Specifications
LTC1531 Self-Powered Isolated Comparator
October 1998
FEATURES
s s s s s s s
DESCRIPTION
The LTC(R)1531 is an isolated self-powered dual differential comparator. An internal capacitive isolation barrier provides 3000VRMS of isolation between the comparator and its output. The part provides UL-rated isolated comparisons without the need for an isolated supply since both comparator power and output data are transmitted across the capacitive barrier. The comparator data is transferred differentially across the isolation barrier to provide high common mode voltage and noise immunity. The isolated side can supply a 2.5V reference output to power external sensor circuits such as a thermistor bridge. The dual differential comparator inputs allow for comparison of two differential voltages as well as single-ended voltages. The powered side provides a latched data output as well as a pulsed zero-cross comparator output for controlling a triac. The part is available in a 28-lead SO package.
Self-Powered Across Isolation Barrier 3000VRMS Isolation 2.5V Isolated Reference, ILOAD = 5mAMAX UL Qualification Pending Zero-Cross Output for Line Power Dual Differential Input Comparator High Input Impedance Comparator
APPLICATIONS
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Self-Powered Isolated Sensing Isolated Temperature Control Isolated Voltage Monitor Isolated Switch Control
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATION
Isolated Thermistor Temperature Controller
AC 120V HEATER 25 TECCOR Q4008L4 OR EQUIVALENT NEUTRAL 150 1k 2N2222 1N4004 2.5k 5W ISOLATION BARRIER R2 47k C1 0.01F COMPARISON V1 - V3 > V4 - V2 R = RO * e B (1/T - 1/TO) B = 3807
R1 680k
390 LED
VCC ZCDATA
SHDN
ZC + ZC -
VPW 2.5V VREG V1 V2
DATA 5.6V
QD
+
100F VALID GND LTC1531 ISOGND
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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+
1F
+ -
V3 V4 CMPOUT HYSTERESIS 1M
THERM 30k YSI 44008
R4 50k
1531 TA01
1
LTC1531
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW VCC SHDN ZCNEG ZCPOS 1 2 3 4 28 GND 27 ZCDATA 26 DATA 25 VALID
Total Supply Voltage (VCC to GND) ............................ 7V Input Voltages Isolated Comparator (V1 to V4) .............................. - 0.3V to (VPW + 0.3V) SHDN, ZCPOS, ZCNEG ......................... - 0.3V to 12V Current Input Pins ....................................................... 10mA ZCDATA, VALID, DATA .................................. 10mA Operating Temperature Range ..................... 0C to 70C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1531CSW
VPW 11 CMPOUT 12 VREG 13 ISOGND 14
18 V1 17 V2 16 V3 15 V4
SW PACKAGE 28-LEAD PLASTIC SO (ISO)
TJMAX = 125C, JA = 125C/ W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL IVCC VZCOS VHYS VCMR f SAMPLE VOS QINJ IVIN VREG RVREG ICMPOUT tVREG VPWH IVPW VISO PARAMETER Supply Current Zero-Cross Offset Zero-Cross Hysteresis Zero-Cross Input Common Mode Range Isolated Comparator Sample Rate Isolated Comparator Offset Isolated Comparator Input Charge Injection Isolated Comparator Input Current VREG VREG Output Impedance CMPOUT High Impedance Leakage Current VREG On-Time VPW, Power Detect Enable Voltage Current Transfer to VPW Isolation Voltage
VCC = 5V, TA = 25C unless otherwise noted.
MIN
q q q
CONDITIONS SHDN = VCC, No Load SHDN = 0V (Note 7) VREG Not Loaded (Note 2) V1 = V2, V3 = V4 V1 - V3 = 2V, V4 - V2 = 2V V1 = V3 = 2.5V, V2 = V4 = 0V (Note 3) V1 = V3 - 2.5V, V2 = V4 = 0V fSAMPLE = 700Hz (Note 4) 2mA Load VPW = 3V (Note 5) 2mA to 5mA Load VCMPOUT = 2.5V
q q q q q
TYP 10 0.2 30 200 300 2.0 2.0 4 1
MAX 14 10 120 800 VCC 4.0 4.0
UNITS mA A mV mV V Hz mV mV pC nA
q q (VCC/2)+0.5
2.40
2.50 4 1
2.55 15 130
90
105 3.3 45 30
VPW = 0V VPW = 3.3V 1 Minute (Note 6) 1 Second
q q
2500 3000
VRMS VRMS
2
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WW
W
V nA s V A A
LTC1531
ELECTRICAL CHARACTERISTICS
SYMBOL VIH VIL VOH VOL IINL, IINH dV/dt PARAMETER SHDN Input High Voltage SHDN Input Low Voltage DATA, VALID, ZCDATA Output High Voltage DATA, VALID, ZCDATA Output Low Voltage SHDN Low or High Level Input Current Continuous dV/dt Rejection
VCC = 5V, TA = 25C unless otherwise noted.
MIN
q q q q q q
CONDITIONS VCC = 4.5V VCC = 5.5V VCC = 4.5V, IO = 400A VCC = 4.5V, IO = 1.6mA VIN = 5V, 0V (Note 8)
TYP
MAX 0.8
UNITS V V V V A V/s
2.4 3.0 4.3 0.2 50 70 0.4 1
The q denotes specifications that apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The sample rate is not continuous, but depends on VPW charging rate. See Applications Information.
Note 3: See Applications Information for further description of the comparator switched-capacitor input circuit. Note 4: The sample rate, fSAMPLE, varies with loading on VPW and VREG. Note 5: Load on CMPOUT pulls current from VREG when CMPOUT is high. Note 6: Value derived from 1 second test. Note 7: Zero-cross hysteresis is the minimum amount of signal amplitude above or below 0V differential to retrigger the zero-cross comparator. Note 8: Parameter not tested but guaranteed by design.
TYPICAL PERFORMANCE CHARACTERISTICS
3.3
VCC = 5V CVPW = 1F IVREG = 5mA TA = 25C VPW
VRIPPLE
tSAMPLE (ms)
2.5
tSAMPLE
VREG (V)
VPW (V)
VREF
0
100 TIME (ms)
200
NOTES: VRIPPLE DEPENDS ON CVPW AND IVPW + IVREG tSAMPLE DEPENDS ON IVPW + IVREG
1531 F01
Figure 1. VPW Power-Up and VREG Samples
UW
300
3.3
VCC = 5V, CVPW = 1F IVREG = 100A, TA = 25C
30 TA = 25C 25 VCC = 4.5V 20 15 10 VCC = 5V 5 VCC = 5.5V
2.5
0 0 10 20 30 TIME (ms) 40
0
0
1
2 IVREG (mA)
3
4
1531 F03
NOTE: NONPERIODIC SAMPLES DUE TO DEPENDENCE ON VPW > 3.3V AND THE POWER-LISTEN CYCLE SAMPLING 1531 F02
Figure 2. VREG and VPW with IVREG = 100A
Figure 3. Average tSAMPLE vs IVREG
3
LTC1531
PIN FUNCTIONS
VCC (Pin 1): Powered Side Power Supply. SHDN (Pin 2): Active Low Chip Shutdown. A low signal causes the circuitry to power down. DATA logic output level will be reset to zero during power-down. ZCNEG (Pin 3): Zero-Cross Comparator Negative Input. ZCPOS (Pin 4): Zero-Cross Comparator Positive Input. VPW (Pin 11): Isolated Power Supply. Tied to an external storage capacitor. CMPOUT (Pin 12): Isolated Latched Comparator Data. CMPOUT is active when VREG is on. The CMPOUT output can be used on the isolated side for hysteresis (see applications). The output will contain the result of the previous comparison. When VREG is low, the CMPOUT pin is Hi-Z. VREG (Pin 13): Isolated 2.5V Regulated Output. Pulsed on for 100s with a maximum load current of 5mA. VREG also supplies power to the CMPOUT output (Pin 12). ISOGND (Pin 14): Isolated Side Power Ground. V4 (Pin 15): Comparator Negative Input. The comparator inputs are summed together with the comparison output equal to (V1 + V2)/2 > (V3 + V4)/2 or equivalently (V1 - V3) > (V4 - V2). V3 (Pin 16): Comparator Negative Input. V2 (Pin 17): Comparator Positive Input. V1 (Pin 18): Comparator Positive Input. VALID (Pin 25): Pulsed Output. Indicates when valid data was received from the comparator. May be used to clock DATA to external circuitry. DATA (Pin 26): Latched Comparator Result. DATA holds the value of the last valid comparison result. DATA changes only when a valid comparison was received from the isolated side. ZCDATA (Pin 27): A 24s to 30s Pulsed Output. The pulse occurs when the DATA output is high and the zerocross comparator inputs (ZCPLS-ZCNEG) cross zero volts differential. Typically the zero-cross input signal is an RC phase shifted AC sine wave. This output is a TTL level pulse that can be used for firing an external triac. GND (Pin 28): Power Supply Low Impedance Ground Connection.
TI I G DIAGRA
VREG CMPOUT Hi-Z
VALID
DATA POWER-LISTEN CYCLE 1152s
4
W
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UW
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POWER CYCLE 960s
LISTEN CYCLE 192s
200ns
POWER
LISTEN
100s
1531 TD01
LTC1531
BLOCK DIAGRAM
POWERED SIDE VCC VCC 1 VOLTAGE PUMP
VALID 25 TIMING
DATA 26
QD R
POWER-ON RESET
ZCDATA 27 CMPOUT 12 ZERO-CROSS COMPARATOR
GND 28
APPLICATIONS INFORMATION
The LTC1531 is an isolated self-powered dual differential comparator. It contains a switched-capacitor comparator that is self-powered through a capacitive isolation barrier. The capacitive isolation barrier provides 3000VRMS of isolation. The isolated comparator duty cycles between storing power and performing comparisons. During the power delivery cycle, the nonisolated powered side delivers power through the internal isolation capacitors and rectifier onto an external storage capacitor. Periodically the isolated comparator makes a comparison if sufficient voltage has been stored on the external supply capacitor. See Timing and Block Diagrams. During a comparison, the isolated side uses the energy stored on the external capacitor to deliver a regulated 2.5V power source for 100s followed by a switched capacitor comparison. The result is transmitted back to the nonisolated powered side and latched, providing a logic level DATA output. A comparison will occur during the listen cycle if sufficient voltage (3.3V) has been stored on the external capacitor. New DATA is latched only if a comparison was actually done. A zero-crossing trigger pulse output, ZCDATA, for firing a triac is available to trigger a triac when the latched DATA output is high. A VALID data output pulse is provided after each powerlisten cycle in which a comparison was done to indicate that DATA has been updated. The VALID data output can be used to clock external circuitry when a new comparator DATA value occurs. Power-Listen Cycle The LTC1531 comparator powered side toggles between delivering power to the isolated side and listening for a comparison result (see Timing Diagram). During the power cycle, AC power is delivered through the isolation capacitors to the isolated side. During the listen cycle, the powered side receives pulses from the isolated side and determines if a valid comparison occurred.
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W
W
ISOLATION BARRIER VPW 11 3.3V DET V1 18 ISOLATED SIDE TRANSMIT AND DRIVER
+
LATCH COMPARE

V2 17 V3 16 V4 15 VREG 13
-
+
TIMING DECODE
-
2.5V REG
4
3
2 SHDN
14 ISOGND
1531 BD
ZCPOS ZCNEG
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5
LTC1531
APPLICATIONS INFORMATION
VPW, External Storage Capacitor and Sample Rate The isolated side of the LTC1531 requires an external capacitor connected to VPW whose value must be large enough to sustain less than a 300mV drop for 100s with the given internal + external VREG load current. Power is delivered to this external capacitor through the internal isolation capacitors and rectifiers during the power cycle. When this voltage reaches approximately 3.3V, the compare circuitry is enabled and a comparison will occur during the next listen cycle. This capacitive coupled isolated power source can be modeled as an equivalent 5V to 6.5V source with a 100k source impedance. This pin will tend to self-regulate at 3.3V with a ripple determined by the discharge current supplied during the 100s VREG output pulse and the external capacitor value. The value of the capacitor affects the initial start-up time and the ripple voltage on VPW, but it does not influence the sample rate of the comparator. Any excessive external DC loading on VPW may prevent the capacitor voltage from reaching the required 3.3V enable voltage. Some continuous micropower loading on VPW can be tolerated based on the 100k, 5.5V model of the power source (see Typical Applications for examples). The quiescent current of the isolated side is around 2A to 3A and the active internal load current is approximately 1mA. The comparator sample rate depends on the charging rate through the isolated capacitors and the external + internal load current . The power-listen cycles at 700Hz to 900Hz, however, a comparison will only occur when VPW exceeds the 3.3V enable voltage. Typical sample rate for light loading is 200Hz to 300Hz. The actual sampling is not uniform, but occurs during the listen period of the power cycle and when VPW 3.3V. Typical sample rates for various supply and load conditions are plotted in Figure 3 in Typical Performance Characteristics section. For maximum power transfer and maximum sample rates, etch copper away from the area shown in Figure 4. Isolated Comparator Inputs and CMPOUT The LTC1531 isolated switched-capacitor comparator has four inputs that allow various differential input sampling modes. All the comparator inputs sample simultaneously during the comparator autozero cycle, then switch to summing them together providing a dual differential comparison. The comparison performs: (V1 + V2)/2 > (V3 + V4)/2 By rearranging the equation, for example, a dual differential comparison is performed: (V1 - V4) > (V3 - V2) or (V1 - V3) > (V4 - V2) The switched-capacitor input samples at one time instance and has a rail-to-rail input and common mode voltage range of VPW -ISOGND. The summing nature of the inputs allows midsupply referencing, for example, by connecting V3 to VREG and V4 to ISOGND which sums together to provide VREG/2 for the negative comparator input, as in the Isolated Switch application. Charge injection occurs at the switched-capacitor comparator inputs. The amount depends on how the comparator is used. Minimum injection occurs with V1 = V2 and V3 = V4. A worst case would be with V1 = 3.3V, V2 = 0V, V3 = 3.3V, V4 = 0V, where the charge injection would be 7pC. Since the comparator is turned on only for the last 10s of the 100s VREG period, the charge injection would occur at about the 90s point. The CMPOUT signal is typically used to provide hysteresis, as in the Isolated Temperature Control application. CMPOUT is the latched result of the previous comparison and is active during the following VREG-on period. CMPOUT is powered by VREG, the internal 2.5V regulated output, and is in high impedance except during the 100s VREGon time. When active, CMPOUT is switched low to ISOGND or high to VREG depending on the stored result of the previous comparison. The stored CMPOUT data is reset on power-up and is not necessarily reset by the powered side SHDN pin except when shutdown results in VPW drooping low enough to trigger a power-on reset on the isolated side.
6
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LTC1531
APPLICATIONS INFORMATION
DATA, VALID, ZCDATA During a power cycle, the VALID signal goes high if a valid comparison was made during the previous listen cycle. VALID goes low at the beginning of the next listen cycle. The low-to-high transition of VALID can be used to clock DATA into external circuitry. In order for a comparison to occur, sufficient power must be stored on the isolated side storage capacitor. The DATA output holds the last received compare result. DATA is reset to zero on power-up and shutdown. The VALID output is held high for one power cycle following a correctly received compare result. The received DATA value from the isolated side contains redundancy to improve noise immunity. The ZCDATA is a 25s output pulse triggered by the zerocross comparator. In order for a pulse to occur, the DATA output must be at logic 1 and the ZCPOS-ZCNEG zerocross comparator input crosses 0V after the input has exceeded the 200mV to 800mV of hysteresis. The zerocross comparator output is typically used to trigger a triac from a 60Hz RC phase shifted AC line signal. The zero-cross comparator inputs, ZCPOS and ZCNEG, allow signal swings to exceed the supply rails. However, the ZCPOS and ZCNEG inputs contain ESD diode protection devices which will clamp input signals that go below GND. The current into the diode should be limited to less than 5mA. The Isolated Temperature Control shows an example phase shift network with attenuation that satisfies these conditons. In this example, with R1 >> R2, the phase shift is set by: R2 * C1 tan()/260Hz and the attenuation R2/R1. In this example, R1 = 1M, R2 = 47k and C1 = 0.01F, provides a 7VPEAK input signal referenced to the 5V VCC, with 10 of phase lag. The positive input voltage should not exceed the 12V maximum rating or the 5mA input current to the ESD diode clamp. Isolation dV/dt The maximum continuous dV/dt across the isolation barrier that will still allow the isolated comparator to operate is 50V/s. Rates of dV/dt greater than this cause the isolated side to not detect when its power cycle has stopped and a comparison should begin. PC Board Layout The PC board layout should not have copper near the lead frame isolation capacitors. The copper reduces the power coupling and power delivery to the isolated side.
TOP VIEW VCC SHDN ZCNEG ZCPOS 1 2 3 4 28 GND 27 ZCDATA 26 DATA 25 VALID
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W
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ETCH COPPER FROM THE SHADED AREA
VPW 11 CMPOUT 12 VREG 13 ISOGND 14
18 V1 17 V2 16 V3 15 V4
SW PACKAGE 28-LEAD PLASTIC SO (ISO)
Figure 4. PC Board Layout Consideration
7
LTC1531
TYPICAL APPLICATIONS
Remote Light-Controlled Switch
AC 120V LAMP TECCOR Q4008L4 OR EQUIVALENT NEUTRAL 150 1k R1 1N4004 680k 2.5k 5W ISOLATION BARRIER R2/(R1 + R2) = ATTENUATION R2 * C1 = Tan()/(260Hz) = DESIRED PHASE LAG
AC 120V LOAD TECCOR Q4008L4 OR EQUIVALENT NEUTRAL 150 1k 1N4004 2.5k 5W
5.6V
R2 10M C2, 1F VCC ZCDATA VCC VOUT 0V TO VCC FULL-SCALE OUTPUT R3 10M VCC VALID 10k GND 10k LTC1531 SHDN ZC
+
LT1490
8
U
R2 47k
C1 0.01F
+
VCC ZCDATA SHDN ZC
+
ZC
-
VPW 2.5V VREG V1 V2
2.2F
CADMIUM LIGHT SENSOR 100k
DATA 5.6V 100F
+ QD -
V3 V4 CMPOUT
+
VALID GND LTC1531 ISOGND
HYSTERESIS 1M
100k
1531 TA02
Isolated Switch Control
R1 680k R2 47k C1 0.01F ISOLATION BARRIER R2/(R1 + R2) = ATTENUATION R2 * C1 = Tan()/(260Hz) = DESIRED PHASE LAG
+
390 LED ZCDATA VCC SHDN ZC
+
ZC
-
VPW 2.5V VREG V1 V2
1F
1M
DATA
QD
+ -
V3 V4 LOW VOLTAGE SWITCH
1531 TA03
+
100F VALID GND LTC1531 ISOGND
CMPOUT
Isolated Voltage Sense
VCC ISOLATION BARRIER RESOLUTION = 4mV SETTLING TIME CONSTANT = 10 sec
+
ZC - VPW 2.5V 2.2F VREG V1 V2 DATA QD + - V3 V4 CMPOUT R1, 1M ISOGND C1 0.22F
1531 TA05
VIN 0V TO 2.5V FULL-SCALE INPUT
- +
LTC1531
TYPICAL APPLICATIONS
Isolated Potentiometer Transducer Sense
VCC R2 10M C2, 1F VCC ZCDATA VCC VOUT 0V TO VCC FULL-SCALE OUTPUT R3 10M VCC VALID 10k GND 10k LTC1531 ISOGND SHDN ZC + ZC - ISOLATION BARRIER RESOLUTION = 4mV SETTLING TIME CONSTANT = 10 sec
LT1490
10M
C1, 1F
ZCDATA VCC 10M VCC VALID 10k GND 10k OP AMP OFFSET ADJUST COLD JUNCTION COMPENSATES 0C TO 60C OUTPUT, VTEMP DEPENDS ON VCC RESOLUTION = 4mV 0.5C RESPONSE TIME = 10 sec LTC1531 ISOGND VTEMP 0V TO VCC 0C TO 200C DATA QD
2.5V
V1 V2 + - V3 V4 CMPOUT R1, 1M
1/2 LT1495
LT1490
GAIN SET FOR 0C TO 200C C2 0.22F
1531 TA07
1/2 LT1495
UNUSED OP AMP CONNECT AS SHOWN TO MINIMIZE POWER CONSUMPTION
Over Temperature Detect
VCC ISOLATION BARRIER
+
2.2F
1M
LT1389-1.2
1.74M THERM 30k YSI 44008 10.8k
10M VCC ZCDATA SHDN ZC
+
ZC -
VPW 2.5V
10.104k
V1 V2 + -
1/2 LT1495
VTRIP
DATA
QD
V3 V4 GAIN SET FOR 0C TO 200C
VALID GND LTC1531 ISOGND
CMPOUT
1531 TA08
1/2 LT1495
+
COLD JUNCTION COMPENSATES 0C TO 60C OUTPUT, VTRIP AT 100C IS ADJUSTABLE RESPONSE TIME = 10 sec RESOLUTION = 4mV 0.5C
UNUSED OP AMP CONNECT AS SHOWN TO MINIMIZE POWER CONSUMPTION
-
-
VREG
33k 1.116k
+ -
K
-
-
+
-
+
+
U
VCC VCC
+
VPW 2.5V 2.2F VREG V1 V2 DATA QD + - V3 V4 CMPOUT R1, 1M C1 0.22F
1531 TA06
100k
- +
- +
Isolated Thermocouple Voltage
ISOLATION BARRIER
+
2.2F
1M
LT1389-1.2
1.74M THERM 30k YSI 44008 10.8k K
10M SHDN ZC
+
ZC -
VPW
VREG
10.104k 33k 1.116k
+
9
LTC1531
TYPICAL APPLICATIONS
Isolated Battery Cell Monitor
5V VCC ZCDATA SHDN ZC
+
CELL 1
DATA
VALID GND LTC1531 ISOGND
ZCDATA
CELL 2
DATA
VALID GND LTC1531 ISOGND
5V VCC ZCDATA SHDN
VLOW
VWINDOW VCC ZCDATA SHDN ZC + ZC - VPW 2.5V VREG V1 V2 VHIGH DATA + QD - V3 V4 VALID WINDOW WIDTH = 1V R1 = R2 (5/WIDTH - 1) GND LTC1531 ISOGND CMPOUT
10
U
VCC
ISOLATION BARRIER
+
ZC - VPW 2.5V VREG V1 V2 + QD - V3 V4 CMPOUT R4 100k R3 180k 2.2F
TO OTHER CELLS
+
+
SHDN ZC + ZC - VPW 2.5V VREG V1 V2 + QD - V3 V4 CMPOUT R1 180k VTRIP = 1.8V R2 100k 2.2F
+
1531 TA04
Isolated Window Comparator
ISOLATION BARRIER
TO OTHER CELLS
+
ZC + ZC - VPW 2.5V VREG V1 V2 DATA + QD - V3 V4 CMPOUT LTC1531 ISOGND 2.2F
VALID GND
+
VIN
-
+
2.2F
R1 400k WIDTH/2 R2 100k
1531 TA09
LTC1531
PACKAGE DESCRIPTION
SW Package 28-Lead Plastic Small Outline Isolation Barrier (Wide 0.300)
(LTC DWG # 05-08-1690)
0.291 - 0.299** (7.391 - 7.595) 0.005 (0.127) RAD MIN 0.010 - 0.029 x 45 (0.254 - 0.737) 0.093 - 0.104 (2.362 - 2.642) 0.037 - 0.045 (0.940 - 1.143)
0.009 - 0.013 (0.229 - 0.330)
NOTE 1 0.016 - 0.050 (0.406 - 1.270)
NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS. *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
U
Dimensions in inches (millimeters) unless otherwise noted.
0.697 - 0.712* (17.70 - 18.08) 28 27 26 25 18 17 16 15
NOTE 1
0.394 - 0.419 (10.007 - 10.643)
1
2
3
4
11
12
13
14
0 - 8 TYP 0.050 (1.270) TYP
0.014 - 0.019 (0.356 - 0.482)
0.004 - 0.012 (0.102 - 0.305)
SW28 (ISO) 0695
11
LTC1531
TYPICAL APPLICATION U
AC Line Overcurrent Detect
VCC ISOLATION BARRIER
+
VCC ZCDATA SHDN ZC + ZC - VPW 2.5V 2.2F VREG V1 V2 VTRIP QD - V3 V4 VALID GND LTC1531 ISOGND CMPOUT 0.01F 1/4 LT1496 1/4 LT1496 1M + 1M AC 50k RSENSE
1M NEGATIVE COMPARATOR INPUT SET TO 1.25V RSENSE IN SERIES WITH AC LINE RSENSE TRIP VOLTAGE = 125mV
900k 50k
1/4 LT1496
UNUSED OP AMP
1/4 LT1496
1531 TA10
RELATED PARTS
PART NUMBER LTC1177 LT1389 DESCRIPTION Isolated MOSFET Driver Nanopower Reference COMMENTS No Secondary Power Supply, 2500VRMS Isolation 800nA, 0.05% Accuracy, 10ppm/C Max Drift 2.1A Typ, 2V to 11V Supply, Adjustable Hysteresis Low Offset 375VMAX, 2.2V to 36V Supply 0.3A Typ, Adjustable Hysteresis, 2V to 11V Supply
LTC1440/LTC1441 Ultralow Power Single/Dual Comparator with Reference LTC1442 LT1495/LT1496 LTC1540 1.5A Max, Dual/Quad Precision Rail-to-Rail Input and Output Op Amps Nanopower Comparator with Reference
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
1531i LT/TP 1098 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1998
- - + + - + - +
DATA
AC

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